1. Field of the Invention
The present invention relates to a DSP (digital signal processing) architecture, and more particularly, to a DSP architecture that provides a wide memory bandwidth according to an image processing algorithm, and a memory mapping method thereof.
2. Description of the Related Art
One among basic functions that are performed by a digital processor is to access a memory for data reading and writing. The memory is generally accessed by an address provided from a digital processor. The memory access operation of the digital processor is greatly influenced by the input-output structure of the memory, and particularly, is closely related to a memory bandwidth which represents the number of data capable of being input/output at one time.
A Digital Signal Processing (hereinafter, referred to as “DSP”) architecture performs image processing such as image enhancement, compression, and decompression. Particularly, in a DSP architecture which processes moving images as shown in FIG. 1, for example, when an algorithm which accesses three frames and creates a new frame is executed, three video image frames 101, 102, and 103, as sources, are stored in a memory 120 through the DSP CE architecture 110, and the three frame data stored in the memory 120 are read out and processed by a calculation element of the DSP architecture 110, thereby creating one frame 130.
Assuming that the DSP architecture 110 processes moving images with a resolution of 1920×1080 pixels at 60 Hz, the number of pixels to be processed per second is 1920×1080×60≈124M. Here, considering R, G, and B color components, the number of pixels to be processed per second is 124M×3=373M. To store the 373M pixels in the memory 120, the access operations between the DSP architecture 110 and the memory 120, that is, writing operations and reading operations should be repeated several times.
Meanwhile, to operate a DSP architecture at a high speed, a Harvard architecture that includes a data path and an instruction path separately is generally used as a DSP architecture. FIGS. 2 through 4 show examples of Harvard architectures used as DSP architectures.
FIG. 2 shows a conventional representative Harvard architecture wherein image data is loaded into data buses, stored in an external SDRAM under the control of an SDRAM controller, and then read out.
However, image data processed by the DSP architecture 200 of FIG. 2 is dependent on the data bandwidth of the memory devices, as seen in FIG. 2. For example, if an algorithm that accesses three frames and creates a new frame is executed according to a three-dimensional de-interlacing method, memory access operations for 8 pixels per one motion check are required, and accordingly, memory access operations for 64 pixels are required since the 8 memory access operations should be performed 8 times in a three-dimension de-interlacing method. Such a memory access operation requires a predetermined cycle time consumed for operations to address memory cells and operations to read cell data. Particularly, in a case of the resolution of 1920×1080 pixels, 24 memory access cycles are necessary if a DSP architecture with an operation speed of 3.0 GHz is used to process 124M pixels. Therefore, it is difficult to process high resolution images due to the existence of such a physical access cycle required to access the memory in the DSP architecture.
Accordingly, to process high resolution images, a new DSP architecture with a wide memory bandwidth is necessary.